VLSI chip design

Author

Gyi, Huang Lin ; Dong, Chen Xiao ; Yin, Xia Wu ; Jiang, Zhu Ya ; Fei, Pan Bang ; Jing, Li ; Hui, Wang Yu

Author_Institution

Centre of Microelectron., Acad. Sinica, Beijing, China

fYear

1996

fDate

21-24 Oct 1996

Firstpage

348

Lastpage

351

Abstract

The developing trends of ASIC are higher speed, higher integrating density, and smaller size. So, such problems as “What are the key points to design VLSI chip successfully?”, “How to fully grasp each step in the design process?”, are what designers focus on. We have searched out a set of methods for VLSI chip design. With these methods, we have successfully designed three VLSI chips. One of them is a sea-of-gate chip containing 22 K gates. It takes 1.2 micron design rules and two-metal-layer Si-gate CMOS process. The die size is 7.9 mm×9.0 mm. The yield is 77%. This chip has been used in practical applications. In this paper, we present our design methods and simulation results

Keywords

CMOS logic circuits; VLSI; application specific integrated circuits; circuit CAD; integrated circuit design; integrated circuit yield; logic CAD; logic arrays; 1.2 micron; ASIC; CMOS process; VLSI chip design; design process; design rules; die size; integrating density; sea-of-gate chip; simulation results; speed; yield; Application specific integrated circuits; Chip scale packaging; Delay effects; Design methodology; Flip-flops; Integrated circuit interconnections; Libraries; Timing; Very large scale integration; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 1996., 2nd International Conference on

Conference_Location

Shanghai

Print_ISBN

7-5439-0940-5

Type

conf

DOI

10.1109/ICASIC.1996.562825

Filename

562825