Title :
1 GHz logic circuits with sense amplifiers
Author :
Takahashi, O. ; Aoki, N. ; Silbermah, J. ; Dhong, S.
Author_Institution :
Res. Lab., IBM Corp., Austin, TX, USA
Abstract :
This paper describes a logic circuit family which is used extensively in 1.0 GHz single-issue 64-bit PowerPC integer processor. The family consists of an incrementor, a count-leading-zero, a rotator, and a ROM. Each macro consists of a leaf-cell array, dual rail bit-lines, a row of sense amplifiers, a control block, and peripheral circuits. A common read out scheme of sensing the differential voltage of dual rail bit-lines is used. The hardware is fabricated in a 0.25 /spl mu/m mask channel length, 6-metal-layer (Al) CMOS technology (1.8 V nom. V/sub DD/).
Keywords :
CMOS logic circuits; integrated circuit design; logic CAD; logic arrays; microprocessor chips; 0.25 micron; 1 GHz; 1.8 V; 64 bit; CMOS technology; IC design; channel length; count-leading-zero; differential voltage; dual rail bit-lines; incrementor; leaf-cell array; logic circuit family; read out scheme; rotator; sense amplifiers; single-issue PowerPC integer processor; Artificial intelligence; CMOS technology; Circuit synthesis; Circuit testing; DH-HEMTs; Hardware; Logic circuits; Rail to rail amplifiers; Read only memory; Voltage;
Conference_Titel :
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4766-8
DOI :
10.1109/VLSIC.1998.688019
