Power management in high-level design

Power is significant concern for any application that distinguishes itself by battery life (e.g., pagers, cellular phones, etc.), but this is not the only power sensitive market. Power management is just as critical for today´s ASIC and IC designers in nearly every market segment. Consider the following: Increased power increases electromigration and reduces reliability in long-life-cycle telecom products. Adding heat sinks or moving from plastic to ceramic packaging significantly increases the cost per unit in high volume´ chips. In deep-submicron design, increasing complexity and higher clock frequencies result in higher power consumption. There are many opportunities in the design process for designers to reduce power consumption. Following is an overview of how designers can reduce power consumption throughout the design process using power analysis and optimization