Title :
Parallel condition-code generation for high-frequency PowerPC microprocessors
Author :
Burns, J.L. ; Nowka, K.J.
Author_Institution :
Res. Lab., IBM Corp., Austin, TX, USA
Abstract :
Improving the speed and performance of microprocessors requires aggressive leveraging of the interplay of microarchitecture and circuit design. We describe a unique, high-frequency dataflow macro for accelerating conditional-branch resolution by computing condition codes in parallel with computing the corresponding arithmetic results. This macro improves the microarchitecture by reducing conditional-branch latency while achieving high speed through a pulse-node, delayed-reset dynamic circuit implementation. The design has been realized in a 64-bit PowerPC integer processor that operates at 1.0 GHz (0.15 micron CMOS process).
Keywords :
CMOS digital integrated circuits; data flow computing; instruction sets; integrated circuit design; microprocessor chips; parallel architectures; 0.15 micron; 1.0 GHz; 64 bit; CMOS process; circuit design; conditional-branch latency; conditional-branch resolution; delayed-reset dynamic circuit implementation; high-frequency PowerPC microprocessors; high-frequency dataflow macro; microarchitecture; parallel condition-code generation; Acceleration; Arithmetic; CMOS process; Circuit synthesis; Concurrent computing; Delay; Microarchitecture; Microprocessors; Power generation; Pulse circuits;
Conference_Titel :
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4766-8
DOI :
10.1109/VLSIC.1998.688020
