Title :
C-testable vector set design for antifuse-based FPGA cell
Author :
Wenyi, Feng ; Rongchang, Yan ; Weikang, Huang
Author_Institution :
Dept. of Electr. Eng., Fudan Univ., Shanghai, China
Abstract :
This paper presents a general approach to C-test antifuse-based FPGA. The C-Testable Vector Set can be derived from the test set of the basic cell. Each different CIN-linked CTVS corresponds to a different interconnection. Also, we proposed a general DFT method to make an arbitrary single output cell C-testable by adding one extra XOR gate and one extra transferring gate per cell. One example illustrates the proposed approaches
Keywords :
design for testability; electric fuses; field programmable gate arrays; logic testing; C-testable vector set; CIN-linked CTVS; DFT; FPGA cell; XOR gate; antifuse; interconnection; transferring gate; Circuit testing; EPROM; Field programmable gate arrays; Hardware; Integrated circuit interconnections; Logic arrays; Logic testing; Programmable logic arrays; Prototypes; Switches;
Conference_Titel :
ASIC, 1996., 2nd International Conference on
Conference_Location :
Shanghai
Print_ISBN :
7-5439-0940-5
DOI :
10.1109/ICASIC.1996.562835
