C-testable vector set design for antifuse-based FPGA cell

This paper presents a general approach to C-test antifuse-based FPGA. The C-Testable Vector Set can be derived from the test set of the basic cell. Each different CIN-linked CTVS corresponds to a different interconnection. Also, we proposed a general DFT method to make an arbitrary single output cell C-testable by adding one extra XOR gate and one extra transferring gate per cell. One example illustrates the proposed approaches