Power consumption of static and dynamic CMOS circuits: a comparative study

Author

Macii, Enrico ; Poncino, Massimo

Author_Institution

Dipt. di Autom. e Inf., Politecnico di Torino, Italy

fYear

1996

fDate

21-24 Oct 1996

Firstpage

425

Lastpage

427

Abstract

The choice of technology to be used for the implementation of a given specification is usually dependent on the optimization and the performance constraints that the finished chip is required to meet. When the target is low-power dissipation, one of the decisions that the designer has to take concerns the use of static versus dynamic CMOS transistors. Although, from the theoretical stand-point, the main advantages and disadvantages of both technologies are quite well established, no experiment-driven guidelines have been provided so far to VLSI designers regarding this specific aspect. In this paper, we present the results of an empirical investigation we have carried out on a large set of benchmarks, and we comment on the experimental evidence

Keywords

CMOS logic circuits; circuit optimisation; combinational circuits; delays; integrated circuit design; integrated circuit measurement; logic testing; power consumption; VLSI design; benchmark circuits; combinational circuits; dynamic CMOS circuits; gate delay effects; low-power dissipation; optimization; performance constraints; power consumption; power dissipation model; static CMOS circuits; CMOS logic circuits; CMOS technology; Capacitance; Capacitors; Clocks; Energy consumption; Power dissipation; Semiconductor device modeling; Switching circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 1996., 2nd International Conference on

Conference_Location

Shanghai

Print_ISBN

7-5439-0940-5

Type

conf

DOI

10.1109/ICASIC.1996.562843

Filename

562843