A CMOS 260 Mbps read channel with EPRML performance

Author

Conway, T. ; Quinlan, P. ; Spalding, J. ; Hitchcox, D. ; Mehr, I. ; Dalton, D. ; McCall, K.

Author_Institution

Analog Devices BV, Limerick, Ireland

fYear

1998

fDate

11-13 June 1998

Firstpage

152

Lastpage

155

Abstract

In this paper, the read channel architecture for a 260 Mbps read channel far magnetic recording applications is presented. The read channel uses a 7 pole 2 zero continuous time filter with a 6 bit flash ADC in the analog front end. The ADC samples are further equalized to the PR4 partial response target with a 5 tap fully asymmetric FIR including LMS adaption. Detection is performed with a PR4 Viterbi detector followed by a postprocessor based on a 16/17(0,6/6) modulation code achieving full EPR4 performance over a range of channel densities. The design is implemented in 0.35 /spl mu/m DPTM CMOS and dissipates 1.3 W max at 260 Mbps.

Keywords

CMOS integrated circuits; FIR filters; Viterbi detection; analogue-digital conversion; continuous time filters; least mean squares methods; magnetic recording; maximum likelihood detection; mixed analogue-digital integrated circuits; partial response channels; 0.35 micron; 1.3 W; 16/17(0,6/6) modulation code; 260 Mbit/s; CMOS read channel; DPTM CMOS; EPRML performance; LMS adaption; PR4 partial response target; Viterbi detector; channel densities; continuous time filter; flash ADC; full EPR4 performance; fully asymmetric FIR; magnetic recording applications; postprocessor; CMOS technology; Delay; Detectors; Disk recording; Finite impulse response filter; Frequency; Least squares approximation; Magnetic separation; Nonlinear filters; Poles and zeros;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-4766-8

Type

conf

DOI

10.1109/VLSIC.1998.688041

Filename

688041