A graph coloring based approach for self-checking logic circuit design

Author

Busaba, Fadi Y. ; Lala, Parag K.

Author_Institution

Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA

fYear

1995

fDate

23-24 Nov 1995

Firstpage

327

Lastpage

330

Abstract

This paper presents a technique for designing self-checking logic circuits by using residue codes. There are no restrictions or assumptions made about the implementation of the circuit. For any single stuck-at fault that causes bi-directional error at the output, all pairs of faulty output lines that show bi-directional errors are identified. Based on the bi-directional dependency between the outputs, a minimum set of residue weights are assigned to the output lines so that any error at the outputs can be detected

Keywords

automatic testing; error detection; fault location; graph colouring; graph theory; integrated circuit testing; integrated logic circuits; logic design; logic testing; bidirectional error; error detection; errors identification; graph coloring; logic circuit design; output lines; residue codes; residue weights assignments; self-checking; single stuck-at fault; Bidirectional control; Circuit faults; Circuit testing; Condition monitoring; Electrical fault detection; Fault detection; Inverters; Logic circuits; Programmable logic arrays; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1995., Proceedings of the Fourth Asian

Conference_Location

Bangalore

Print_ISBN

0-8186-7129-7

Type

conf

DOI

10.1109/ATS.1995.485356

Filename

485356