Current and charge estimation in CMOS circuits

Author

Dhar, Sanjay ; Gurney, Dave J.

Author_Institution

Mentor Graphics Corp., Wilsonville, OR, USA

fYear

1995

fDate

29 Aug-1 Sep 1995

Firstpage

13

Lastpage

18

Abstract

CMOS circuits have significant amounts of dynamic short-circuit (or through) current. This can be as large as 20% of the total in well-designed circuits, and up to 80% of the total in circuits that have not been designed carefully. This current depends strongly on the relative sizes of the pull-up to pull-down paths. We introduce the dynamic short-circuit ratio to model this parameter. This allows accurate estimation of currents including the dynamic short-circuit current, and also results in improved delay estimation. Accuracy is typically within 10% of circuit-level simulation while operating at the switch-level abstraction

Keywords

CMOS digital integrated circuits; circuit CAD; circuit analysis computing; delays; integrated circuit design; integrated circuit modelling; short-circuit currents; CMOS circuits; charge estimation; circuit-level simulation; delay estimation; dynamic short-circuit current estimation; dynamic short-circuit ratio; pull-down paths; pull-up paths; switch-level abstraction; Capacitance; Circuit noise; Circuit simulation; DH-HEMTs; Delay estimation; Driver circuits; Energy consumption; Fabrication; Graphics; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal

Conference_Location

Chiba

Print_ISBN

4-930813-67-0

Type

conf

DOI

10.1109/ASPDAC.1995.486195

Filename

486195