General Model for the Deployment of Time-Delay Elements in Transistorized Electronic Circuits

This paper presents a general model for the analysis of time-delay contributions due to right half plane (RHP) zeros in circuit´s transfer functions. The presence of these RHP zeros is in general associated to Miller capacitances. These can be explored as a means of implementation of delay elements. A general discussion on the usage of these RHP zeros as means of designing usable delay cells is addressed, including several parasitic effects that may arise in practical implementations. The model is then verified recurring to simulation experiments.