Title :
Wafer level defect density distribution using checkerboard test structures
Author :
Hess, Christopher ; Weiland, Larg H.
Author_Institution :
Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
Abstract :
Defect density distributions play an important role in process control and yield prediction. To improve the accuracy in modeling of defect density distributions, we present a wafer level methodology to analyze defect data measured anywhere on a wafer. The inspected area may thus be limited to test structures that just cover a fraction of each wafer. For that, imaginary wafer maps are generated for a variety of different chip areas to calculate a yield-to-area dependency. Based on these calculations, a micro density distribution (MDD) is determined for each wafer that reflects the degree of defect clustering. The single MDDs per wafer may be summarized to also provide a general defect density distribution per lot or any other sample size
Keywords :
failure analysis; integrated circuit testing; integrated circuit yield; process control; production testing; semiconductor process modelling; checkerboard test structures; chip area; defect clustering; defect data; defect density distribution; defect density distribution modeling; general defect density distribution; imaginary wafer maps; inspected area; micro density distribution; process control; sample size; test structures; wafer level defect density distribution; wafer level methodology; yield prediction; yield-to-area dependency; Circuits; Data analysis; Density measurement; Electric variables measurement; Fault tolerance; Manufacturing processes; Process control; Semiconductor device measurement; Semiconductor device modeling; Testing;
Conference_Titel :
Microelectronic Test Structures, 1998. ICMTS 1998., Proceedings of the 1998 International Conference on
Conference_Location :
Kanazawa
Print_ISBN :
0-7803-4348-4
DOI :
10.1109/ICMTS.1998.688050