A Low-Voltage CMOS LNA Design Utilizing the Technique of Capacitive Feedback Matching Network

Author

Wu, Chung-Yu ; Shahroury, Fadi Riad

Author_Institution

Nat. Chiao Tung Univ., Hsinchu

fYear

2006

fDate

10-13 Dec. 2006

Firstpage

78

Lastpage

81

Abstract

In this paper, a CMOS low noise amplifier (LNA) with a new input matching topology has been proposed, analyzed, and measured. The input matching network is designed through the technique of capacitive feedback matching network. The proposed LNA which is implemented in a 0.18-mum 1P6M CMOS technology is operated at the frequency of 12.8 GHz. It has a gain S21 of 13.2 dB, a noise figure (NF) of 4.57 dB and an NF _min of 4.46 dB. The reverse isolation S12 of the LNA can achieve -40 dB and the input and output return losses are better than -11 dB. The input 1-dB compression point is -11 dBm. This LNA drains 10 mA from the supply voltage of 1 V.

Keywords

CMOS analogue integrated circuits; feedback amplifiers; impedance matching; low noise amplifiers; microwave amplifiers; network topology; CMOS LNA design; CMOS low noise amplifier; CMOS technology; capacitive feedback matching network; current 10 mA; frequency 12.8 GHz; gain 3 dB; input matching network topology; microwave amplifiers; noise figure 4.57 dB; reverse isolation; size 0.18 mum; voltage 1 V; CMOS technology; Feedback; Frequency; Impedance matching; Isolation technology; Low-noise amplifiers; Network topology; Noise figure; Noise measurement; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on

Conference_Location

Nice

Print_ISBN

1-4244-0395-2

Electronic_ISBN

1-4244-0395-2

Type

conf

DOI

10.1109/ICECS.2006.379705

Filename

4263308