Title :
SEL-TM: Selective Eager-Lazy Management for Improved Concurrency in Transactional Memory
Author :
Zhao, Lihang ; Choi, Woojin ; Draper, Jeff
Author_Institution :
Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA, USA
Abstract :
Hardware Transactional Memory (HTM) systems implement version management and conflict detection in hardware to guarantee that each transaction is atomic and executes in isolation. In general, HTM implementations fall into two categories, namely, eager systems and lazy systems. Lazy systems have been shown to exploit more concurrency from potentially conflicting transactions. However, lazy systems manage a transaction´s entire write set lazily, which gives rise to two main disadvantages: (a) a complex cache protocol and implementation are required to maintain the speculative modifications, and, (b) the latency of committing the entire write set often leads to severe performance degradation of the whole system. It is observed in a wide range of workloads that more than 55% of the transaction aborts are due to conflicts on only three memory blocks. Thus we argue that an eager HTM system can achieve the same level of concurrency as lazy systems by managing only a small portion of a transaction´s write set lazily. In this paper, we present Selective-Eager-Lazy HTM (SEL-TM), a new HTM implementation to adopt complementary version management schemes within a transaction whose write set is divided into eagerly- and lazily-managed memory addresses at runtime. An intelligent hardware scheme is designed to select the memory addresses for lazy management as well as determining whether each dynamic instance of a transaction benefits from hybrid management. Experimental results using the STAMP benchmarks show that, on average, SEL-TM improves performance by 14% over an eager system and 22% over a lazy system. The speedup demonstrates that our design is capable of harvesting the concurrency benefit of lazy version management while avoiding some of the performance penalties in lazy HTMs.
Keywords :
cache storage; concurrency control; configuration management; transaction processing; HTM system; SEL-TM; STAMP benchmark; complex cache protocol; concurrency; conflict detection; eager system; eagerly-managed memory addresses; hardware transactional memory; hybrid management; intelligent hardware scheme; lazily-managed memory addresses; lazy system; lazy version management; memory block; performance degradation; selective eager-lazy management; selective-eager-lazy HTM; transaction write set; Buffer storage; Concurrent computing; Hardware; Instruction sets; Memory management; Pathology; Runtime; Conflict Point Discovery; Hardware Transactional Memory; SEL-TM; Version Management;
Conference_Titel :
Parallel & Distributed Processing Symposium (IPDPS), 2012 IEEE 26th International
Conference_Location :
Shanghai
Print_ISBN :
978-1-4673-0975-2
DOI :
10.1109/IPDPS.2012.19