Designs of counters with near minimal counting/sampling period and hardware complexity

We propose several synchronous counter designs that have high counting and sampling rates and low cost at the same time. We first present carry-select counters which improve the maximum counting and sampling rates of previous counters based on carry anticipation by a factor of about 2, while requiring similar cost, or reduce the hardware cost of the fastest counters proposed thus far by a factor of about 2, while achieving comparable counting/sampling rate. We then propose a novel technique called postponed readout to further reduce the counting/sampling period to the delay of a 2-input AND gate plus the time for loading a flip-flop, while requiring similar cost. The resultant counting/sampling is competitive with the fastest previous designs and is achieved at a hardware cost that is lower by a factor of about 2. The price paid is that the count is read out 2 or 3 cycles later (depending on the length of the counter), instead of 1 cycle in previous synchronous counters.