New characterization methodology for flash memory cell using CAST structure

Author

Fan, Mcdonald ; Liu, U.C. ; Guo, J.C. ; Wang, M.T. ; Shone, F.

Author_Institution

Dept. of Device, Macronix Int. Co. Ltd., Hsinchu, Taiwan

fYear

1998

fDate

23-26 Mar 1998

Firstpage

113

Lastpage

117

Abstract

Hole trapping occurred during program/erase (P/E) operation in a flash EEPROM. To the authors´ knowledge, there is still no effective method for characterization of the endurance performance of flash EEPROMs at the key test level. In this paper, we propose a simple and fast method to evaluate the endurance performance of a 12 kbit flash EEPROM cell array stress test (CAST) structure. Based on this method, we can easily detect subtle defects as well as the effectiveness of the hole detrapping method used to suppress the tail-bits

Keywords

EPROM; hole traps; integrated circuit reliability; integrated circuit testing; 12 kbit; CAST structure characterization methodology; defect detection; endurance performance; flash EEPROM; hole detrapping method; tail-bit suppression; test flash EEPROM cell array stress test structure; Circuit testing; Current measurement; Dielectrics; EPROM; Flash memory; Flash memory cells; Ink; Product development; Stress; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1998. ICMTS 1998., Proceedings of the 1998 International Conference on

Conference_Location

Kanazawa

Print_ISBN

0-7803-4348-4

Type

conf

DOI

10.1109/ICMTS.1998.688052

Filename

688052