Title :
An Efficient Bit-Detection and Timing Recovery Circuit for FPGAs
Author :
Zicari, Paolo ; Corsonello, Pasquale ; Perri, Stefania
Author_Institution :
Univ. of Calabria, Arcavacata di Rende
Abstract :
In integrated all-digital FPGA based communication systems bit synchronization is a fundamental operation for the best symbol detection. In this paper a highly flexible early-late gate implementation is proposed. It is optimized for low resource consumption in FPGA implementations.
Keywords :
clocks; detector circuits; field programmable gate arrays; timing circuits; communication systems bit synchronization; efficient bit-detection circuit; highly flexible early-late gate; integrated all-digital FPGA; symbol detection; timing recovery circuit; Circuits; Clocks; Computer architecture; Data mining; Detectors; Digital filters; Field programmable gate arrays; Frequency synchronization; Phase detection; Timing;
Conference_Titel :
Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on
Conference_Location :
Nice
Print_ISBN :
1-4244-0395-2
Electronic_ISBN :
1-4244-0395-2
DOI :
10.1109/ICECS.2006.379746
