Design Space Exploration of Division over GF(2m) on FPGA: A Digit-Serial Approach

In this work, the practical improvements in latency for division over GF(2^m) are explored. Elliptic curve cryptography (ECC) hardware accelerators often require low-latency, flexible divider architectures for implementation in FPGA technology. Architectures based on the extended Euclidean algorithm (EEA) are implemented using a digit-serial approach, and the design space is explored using empirical data gained from implementations. Results show that the digit-serial approach leads to improved performance; the fastest implementation in the literature is presented for variable fields m les 255 and for the fixed field GF(2¹⁹³).