High Throughput Architecture of JPEG Compressor for Color Images Targeting FPGAs

This paper presents the design of a JPEG compressor for color images targeting high performance in a low cost FPGA device. The JPEG compressor architecture achieves high throughput with a deep and optimized pipeline and with a multiplierless datapath architecture. The architecture was synthesized to Altera FPGAs and the synthesis results and relevant performance comparisons with related works are presented. Our high throughput compressor for color images is able to compress 39.6 millions of samples per second when mapped onto an Altera FLEX 10KE low cost FPGA. Our JPEG encoder is able to compress 38 color images per second in SDTV resolution (720x480 pixels). Considering this SDTV resolution our design is worthy as a core of an M-JPEG video compressor, reaching a real time processing rate.