Double level interconnection system for submicron CMOS applications

Author

Higelin, G. ; Fritsch, U. ; Küsters, K.H. ; Enders, G. ; Müller, W.

Author_Institution

Siemens AG, Munich, West Germany

fYear

1988

fDate

13-14 June 1988

Firstpage

29

Lastpage

34

Abstract

A double-level interconnection system for severe topography and fine-line submicron lithography has been developed. This system is suitable for single and double poly logic or memory interconnection. It has been successfully applied in Siemens 4-M DRAM with double poly topography. The first interconnection level is realized by a polycide layer with a minimum pitch of 1.7 mu m. The bitline contacts are self-aligned to gate and field oxide. The first level is planarized by a flowglass process using a highly doped borophosphosilicate glass. In the second interconnection level, a Ti/TiN/AlSi barrier metallisation with minimum pitch of 1.8 mu m is used. A contact-filling process using nonselective CVD-W and etchback technique has also been developed for incorporation into this metallization system.<>

Keywords

CMOS integrated circuits; VLSI; integrated circuit technology; metallisation; 1.7 micron; 1.8 micron; DRAM; Ti-TiN-AlSi; W; bitline contacts; borophosphosilicate glass; contact-filling process; double poly topography; double-level interconnection system; etchback technique; fine-line submicron lithography; flowglass process; logic interconnection; memory interconnection; metallisation; nonselective CVD; pitch; planarisation; polycide layer; severe topography; submicron CMOS applications; Boron; CMOS technology; Contact resistance; Dielectrics and electrical insulation; Etching; Lithography; Metallization; Random access memory; Tin; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Multilevel Interconnection Conference, 1988. Proceedings., Fifth International IEEE

Conference_Location

Santa Clara, CA, USA

Type

conf

DOI

10.1109/VMIC.1988.14173

Filename

14173