Design of DCT_2D toward FPGA

Author

Kachouri, Rostom ; Abid, Mohamed ; Amar, C.B.

Author_Institution

Micro-technology & Syst. on chip Group, ENIS, Sfax, Tunisia

fYear

2004

fDate

21-24 March 2004

Firstpage

713

Lastpage

716

Abstract

Long term objective is to conceive a system on chip of the JPEG coding chain. This article presents the VHDL specification, simulation and also synthesis results, of the two-dimensional discrete cosine transform DCT_2D, which constitutes the first block of the JPEG chain. For that, we kept LOEFLER´s algorithm which is the best for the DCT implementation, according to a comparison with other architectures. And we targeted the FPGAs as integration technology. Besides, seeing that the DCT is separable as transformation, the two-dimensional discrete cosine transform (DCT_2D) can be formed by two one-dimensional discrete cosine transform (DCT_1D).

Keywords

data compression; discrete cosine transforms; electronic engineering computing; field programmable gate arrays; hardware description languages; image coding; transform coding; DCT implementation; FPGA; JPEG coding chain; LOEFLER algorithm; VHDL specification; field programmable gate array; hardware description language; joint photographic experts group; one-dimensional discrete cosine transform; two-dimensional discrete cosine transform; Codecs; Data compression; Discrete cosine transforms; Field programmable gate arrays; Frequency; Image coding; Image reconstruction; Machine intelligence; System-on-a-chip; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Control, Communications and Signal Processing, 2004. First International Symposium on

Print_ISBN

0-7803-8379-6

Type

conf

DOI

10.1109/ISCCSP.2004.1296511

Filename

1296511