Design of Reliable CMOS Phase-Locked Loops

Gate-oxide defect is the major cause of the reliability problems for CMOS ICs. The common practice for reliability enhancement is the use of extreme-voltage screening and then the high-temperature burn-in screening, where the Iddq-test approach is generally used to generate the stress vectors for the extreme-voltage screening. Note that the burn-in screening may increase the manufacturing cost ranging from 5% to 40% of the total product cost. This paper demonstrates that a conventional PLL (phase-locked loop) may pass the above screening methods in the presence of gate-oxide defects. This causes a low reliability. Based on an alternative extreme-voltage test scheme, this study presents the generation of stress vector set for developing a fully stress able PLL. With slight modification of the original PLL, a reliable CMOS PLL design is presented to enhance gate-oxide reliability.