Reliability modeling of chip scale packages

The chip-scale package (CSP) is an increasingly popular small size, high performance package. The advantages of such a package are that it offers considerable space savings over full-sized BGA or peripherally leaded devices while maintaining the convenience and die protection of a packaged device. In this paper, a finite element based approach for estimating CSP thermal cycling reliability is presented. The methodology is based on Anand´s viscoplastic constitutive law for solder response and Darveaux´s crack growth rate model for solder fatigue. A Weibull two-parameter failure distribution is assumed. 3D finite element models are built for several different CSP package configurations. Two- and three-fold symmetry is used to reduce the model size and computer run-time. In addition, to facilitate rapid development of the finite element models, a basic building block approach is used. These building blocks consisted of a solder joint (including pad dimensions) and package geometry. These units are then used repeatedly to construct the overall model. The number of cycles to 50% package reliability is estimated for a 20 minute air-to-air thermal profile of 0°C to 100°C (5 minute dwells at each temperature extreme). Good correlation between measured and predicted life is observed. All of the packages studied have measured life within the expected ± 1.5× error band of the method for the Weibull slopes considered