Thru-silicon interconnect technology

Wafer-level packaging (WLP) is forecast to be less expensive than die-level packaging, though many fundamentally new technologies are needed to fulfil this potential. For a complete WLP process flow to be cost-effective, all newly developed technologies should be simple and inexpensive to implement in high-volume manufacturing. Chip-scale packages (CSPs) produced with a WLP process flow are particularly advantageous when combined with flip-chip/BGA connections, since direct-chip attach (DCA) parts can thus be produced entirely by a wafer-fab. A new process technology-atmospheric downstream plasma (ADP) gas etching-allows for the WLP formation of backside thru-silicon contacts for DCA applications. Thru-silicon designs and manufacturing process flows are introduced as means to produce 3D wafer level packaging solutions. Standard silicon IC manufacturing unit-processes must be combined into robust process-flows to allow for the rapid deployment of wafer-level packaging throughout the industry