Author :
Li, Yuan ; Pannikkat, Anil ; Anderson, Larry ; Verma, Tarun ; Euzent, Bruce
Author_Institution :
Altera Corp., San Jose, CA, USA
Abstract :
To provide the benefits of higher I/O density, smaller feature size, and better electrical performance, a full-array 1.0-mm pitch BGA package family were developed. Three package options, termed A, B and C, were investigated. Each of these options has its own advantages and disadvantages. The moire interferometry technique was used to measure the effective coefficient of thermal expansion (CTE) of these three options. To more efficiently access package reliability, a three-dimensional nonlinear finite element method was established. This method has shown good accuracy in predicting solder joint reliability. Using this method, various factors were studied, including die size, package size, package pad opening size, board pad size, solder ball size, die attach thickness, pad design, substrate thickness and board thickness. These studies have given us a good understanding of the effect of each factor and directions for improving solder joint reliability. The optimum parameter settings were selected for the packages. Finite element modeling was used to determine solder joint reliability of the three package options versus die size and package size. Thus, a roadmap of solder joint reliability vs. substrate technology, die size and package size was established. From this roadmap, a preset reliability goal can always be achieved by choosing the right combination of substrate, die and package size
Keywords :
ball grid arrays; finite element analysis; integrated circuit interconnections; integrated circuit modelling; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; light interferometry; microassembling; moire fringes; soldering; thermal expansion; 1 mm; 3D nonlinear finite element method; BGA package pitch; CTE; I/O density; board pad size; board thickness; coefficient of thermal expansion; die attach thickness; die size; electrical performance; feature size; finite element modeling; full-array BGAs; moire interferometry; optimum parameter settings; package options; package pad opening size; package reliability; package size; pad design; preset reliability goal; reliability; solder ball size; solder joint reliability; substrate technology; substrate thickness; Assembly; Electronic packaging thermal management; Electronics packaging; Finite element methods; Materials science and technology; Quality management; Reliability engineering; Semiconductor device packaging; Soldering; Surface-mount technology;
