Design of an Area-Efficient Multiplierless Processing Element For Fast Two Dimensional Image Convolution

Two dimensional (2D) image convolution is a typical algorithm executed by window-based spatial domain filters, which are in turn used in many applications including intrusion detection. Systolic arrays have been widely used in them by exploiting the hardware parallelism on FPGAs to increase the throughput of the system. These implementations differ mostly in the processing element (PE) architecture employed. We propose a new scheme for the PE in the systolic array architecture which uses a novel area-time efficient lookup table (LUT) based method and reduces the LUT resource usage by almost 50% when compared to the conventional constant coefficient LUT based method.