• DocumentCode
    2959426
  • Title

    Performance monitoring and tuning for a single-chip multiprocessor digital signal processor

  • Author

    Kim, Jihong ; Kim, Yongmin

  • Author_Institution
    Texas Instrum. Inc., Dallas, TX, USA
  • fYear
    1996
  • fDate
    11-13 Jun 1996
  • Firstpage
    76
  • Lastpage
    83
  • Abstract
    A new generation of high performance programmable digital signal processors (DSPs) has a highly-integrated parallel architecture, incorporating special-purpose hardware features, on-chip memory and multiple processors into a single chip. For such single-chip multiprocessor DSPs, however, a sophisticated performance monitoring tool is essential to achieve the maximum performance. The authors discuss the requirements and functionality of performance monitoring tools suitable for single-chip multiprocessor DSPs. As a specific example, they describe a performance monitoring tool developed for Texas Instruments´ TMS320C80 (MVP), MVP Performance Monitor (MPM), which satisfies these requirements and functionality. The effectiveness of the MPM is demonstrated using an 8×8 block-based discrete cosine transform (DCT) implementation. An overall speed-up of 4.67 was achieved by using the MPM
  • Keywords
    circuit tuning; computer testing; digital signal processing chips; discrete cosine transforms; integrated circuit testing; multiprocessing systems; parallel architectures; performance evaluation; MVP Performance Monitor; Texas Instruments TMS320C80; block-based discrete cosine transform; high performance programmable digital signal processors; highly-integrated parallel architecture; multiple processors; on-chip memory; performance monitoring tool; performance tuning; single-chip multiprocessor digital signal processor; special-purpose hardware features; speed-up; Application software; Digital signal processing; Digital signal processing chips; Digital signal processors; Discrete cosine transforms; Hardware; Instruments; Monitoring; Parallel architectures; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Algorithms & Architectures for Parallel Processing, 1996. ICAPP 96. 1996 IEEE Second International Conference on
  • Print_ISBN
    0-7803-3529-5
  • Type

    conf

  • DOI
    10.1109/ICAPP.1996.562860
  • Filename
    562860