DocumentCode
2959460
Title
Designed experiment to assess the surface mount attachment reliability of 14 mil pitch (1000 I/O) underfilled DCA
Author
Yegnasubramanian, S. Mani ; Deshmukh, R. ; Rubin, H.D. ; Fanucci, R. ; Gannon, J.E. ; Serafino, A. ; Slabinski, B. ; Occhipinti, M. ; Morris, J.R. ; Noctor, D.M. ; Wolf, R.K.
Author_Institution
Lucent Technol., Princeton, NJ, USA
fYear
2000
fDate
2000
Firstpage
200
Lastpage
206
Abstract
To accommodate increasing I/O and maintain die sizes at as small as practicable levels, the use of area array solder bump flip chip is increasingly being used to bond large ASIC and microprocessor devices to a BGA substrate. In conjunction with thermal cycling, an orthogonal array design with different combinations of assembly choices and underfill materials has proven useful in screening material and assembly parameter choices for these high I/O flip chip applications. Preliminary failure mode analysis (FMA) of assemblies subjected to thermal stress was carried out using metallurgical cross sections and CSAM examinations of the failed devices. Underfill delamination from the chip surface is the primary cause of failure, even though several other failure modes were also seen. The highest characteristic lives were found using the thin film applicator (TFA) technique in combination with underfill A. Reducing flux residues below the level found using the TFA technique did not significantly improve performance
Keywords
acoustic microscopy; application specific integrated circuits; ball grid arrays; delamination; design of experiments; encapsulation; failure analysis; fine-pitch technology; flip-chip devices; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; microassembling; surface contamination; surface mount technology; thermal stresses; ASIC; BGA substrate; CSAM; DCA pitch; TFA technique; area array solder bump flip chip; assembly; assembly parameter choice; characteristic lives; chip surface; designed experiment; die size; failed devices; failure mode analysis; failure modes; flux residues; high I/O flip chip applications; material choice; metallurgical cross sections; microprocessor devices; orthogonal array design; package I/Os; primary failure cause; surface mount attachment reliability; thermal cycling; thermal stress; thin film applicator technique; underfill delamination; underfill materials; underfilled DCA; Application specific integrated circuits; Assembly; Bonding; Delamination; Failure analysis; Flip chip; Microprocessors; Substrates; Thermal stresses; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Manufacturing Technology Symposium, 2000. Twenty-Sixth IEEE/CPMT International
Conference_Location
Santa Clara, CA
ISSN
1089-8190
Print_ISBN
0-7803-6482-1
Type
conf
DOI
10.1109/IEMT.2000.910729
Filename
910729
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