Inductance calculation and optimal pin assignment for the design of pin grid array and chip-carrier packages

A methodology for calculation of self- and mutual inductance of various electrical paths in a pin grid array (PGA) or a chip carrier package is described. For the highest speed and minimum memory storage requirements, closed-form expressions for inductance are used. An N ×N inductance matrix is generated for a package, where N is determined by the number of pins and the power and ground planes. Theory and algorithms for computing the effective inductance of multiply coupled inductors are described. Using these algorithms, a Fortran program for the design of low-inductance PGA and chip-carrier packages is developed. The software estimates the number of pins for a specified value of inductance and computes the effective inductance for the sets of pins chosen for various functions. In this manner, several groups of pin assignments can be evaluated to obtain the smallest effective inductance. Examples for pin assignments for power and ground pins in single- and multilayer packages are illustrated. Good agreement between calculation and experiment was found for packages with pin count varying from 68 to 289