Title :
Delay Efficient 32-bit Carry-Skip Adder
Author :
Lin, Yu Shen ; Radhakrishnan, Damu
Author_Institution :
State Univ. of New York, New Paltz
Abstract :
The design of a 32-bit carry-skip adder to achieve minimum delay is presented in this paper. The group generate and group propagate functions used in carry look ahead logic are used to speed up multiple stages of ripple carry adders. The optimum sizes for the skip blocks are decided by considering the critical path into account. The adder is implemented in 0.25 mum CMOS technology at 3.3 V. The simulation results showed a critical path delay of 3.4 ns, which translates to a speed improvement of 18% compared to the current fastest carry skip adder.
Keywords :
CMOS logic circuits; adders; carry logic; delay circuits; CMOS technology; carry look ahead logic; carry-skip adder; critical path delay; group generate functions; group propagate functions; ripple carry adders; size 0.25 mum; time 3.4 ns; voltage 3.3 V; word length 32 bit; Acceleration; Added delay; Adders; CMOS logic circuits; CMOS technology; Design optimization; Digital arithmetic; Power dissipation; Signal design; Signal generators;
Conference_Titel :
Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on
Conference_Location :
Nice
Print_ISBN :
1-4244-0395-2
Electronic_ISBN :
1-4244-0395-2
DOI :
10.1109/ICECS.2006.379836
