Engineering multirate convolutions for radar imaging

We present a schematic design methodology for multirate convolution systems, based on combined algorithmic development and architecture design. It allows us to map the algebraic specification of a long convolution algorithm directly onto efficient fast convolution hardware based on short FFT processor elements or dedicated VLSI processors. The design methodology exploits the known relationship between multirate filter banks and fast convolution schemes in an implicit manner, and allows the hardware designer to concentrate on typical application specific constraints such as processing speed, processor size and memory utilization. The methodology has proven its usefulness in the design of a convolution processor for real-time on-board synthetic aperture radar imaging