Title :
Cascade error projection: an efficient hardware learning algorithm
Author_Institution :
Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
Abstract :
A new learning algorithm, termed cascade error projection (CEP), which provides efficient learning in hardware is presented. This algorithm is adapted a constructive architecture from cascade correlation and the dynamical stepsize of A/D conversion from the cascade backpropagation algorithm. The CEP technique is faster to execute, because part of the weights are deterministically obtained, and the learning of the remaining weights from the inputs to the hidden unit is performed as a single-layer perceptron learning with previously determined weights kept frozen. In addition, one can start out with zero weight values when the learning of each layer is commenced. Further, unlike cascade correlation algorithm, only a single hidden unit is added at a time. Therefore, the simplicity in hardware implementation is also achieved. In simulation, a fixed 100 epoch iterations is used for each single-layer perceptron learning. The highlight of this algorithm is that with round-off method, 5- to 8-bit parity problems can be solved with a limited synaptic resolution of only 3- to 4-bit, and the same problem with truncation technique would be solved with 5-bit or more synaptic resolution
Keywords :
analogue-digital conversion; backpropagation; iterative methods; neural net architecture; perceptrons; A/D conversion; architecture; cascade backpropagation; cascade correlation; cascade error projection; iterations; learning algorithm; single-layer perceptron; Backpropagation; Backpropagation algorithms; Hardware; Laboratories; Microelectronics; Neural networks; Pattern recognition; Propulsion; Quantization; Space technology; Speech recognition;
Conference_Titel :
Neural Networks, 1995. Proceedings., IEEE International Conference on
Conference_Location :
Perth, WA
Print_ISBN :
0-7803-2768-3
DOI :
10.1109/ICNN.1995.488088