Synaptic weight generation in VLSI stochastic neural networks

Author

Ortega, J.G. ; Quero, J.M. ; Janer, C.L. ; Franquelo, L.G.

Author_Institution

Escuela Superior de Ingenieros, Seville, Spain

Volume

1

fYear

1995

fDate

Nov/Dec 1995

Firstpage

179

Abstract

Fully parallel stochastic neural network implementations can be realized nowadays. However, in these implementations most of the silicon area is consumed in the stochastic pulse sequence generation circuits. In order to improve their efficiency in terms of consumed silicon area, new techniques must be developed. This is specially important in applications where a large number of synaptic weights are needed. In this paper we present a new approach that can significantly increase the efficiency of the technique that has been used up to now

Keywords

VLSI; integrated logic circuits; neural chips; neural net architecture; oscillators; probabilistic logic; sequential circuits; VLSI; oscillators; stochastic logic; stochastic neural networks; stochastic pulse sequence generation circuits; synaptic weight generation; Circuits; Clocks; Intelligent networks; Multi-layer neural network; Neural networks; Pulse circuits; Pulse generation; Silicon; Stochastic processes; Stochastic systems; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Networks, 1995. Proceedings., IEEE International Conference on

Conference_Location

Perth, WA

Print_ISBN

0-7803-2768-3

Type

conf

DOI

10.1109/ICNN.1995.488089

Filename

488089