DocumentCode
2959755
Title
Yield prediction models for optimization of high-speed micro-processor manufacturing processes
Author
Kim, Tae Seon ; Ahn, Se Hwan ; Jang, Young Gyun ; Lee, Jeong In ; Lee, Kil Jae ; Kim, Byeong Yun ; Cho, Chang Hyun
Author_Institution
Samsung Electron. Co., Yongin, South Korea
fYear
2000
fDate
2000
Firstpage
368
Lastpage
373
Abstract
Neural network based yield prediction models are developed to optimize high-speed microprocessor manufacturing processes. Based on sixty measured ET (electrical test) data, wafer level parametric yield prediction models are developed. In this work, manufacturing yield was considered as a manufacturing performance index because it is critical to overall manufacturing cost and product quality. The prediction results show 41.09% improvement as compared to a statistical prediction model using multiple regression. These modeling approaches are applied to predict final chip yield and speed, and ultimately, this neural prediction model is used to find optimal process conditions. With the successful implementation of this work, it can serve as a catalyst to improve productivity and product quality
Keywords
electronic engineering computing; high-speed integrated circuits; integrated circuit modelling; integrated circuit testing; integrated circuit yield; microprocessor chips; neural nets; optimisation; production testing; quality control; chip speed; final chip yield; high-speed micro-processor manufacturing processes; manufacturing cost; manufacturing performance index; manufacturing yield; measured electrical test data; microprocessor manufacturing processes; modeling approaches; multiple regression; neural network based yield prediction models; neural prediction model; optimal process conditions; optimization; product quality; productivity; statistical prediction model; wafer level parametric yield prediction models; yield prediction models; Costs; Electric variables measurement; Manufacturing processes; Microprocessors; Neural networks; Performance analysis; Predictive models; Productivity; Semiconductor device modeling; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Manufacturing Technology Symposium, 2000. Twenty-Sixth IEEE/CPMT International
Conference_Location
Santa Clara, CA
ISSN
1089-8190
Print_ISBN
0-7803-6482-1
Type
conf
DOI
10.1109/IEMT.2000.910748
Filename
910748
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