Improved-Booth encoding for low-power multipliers

This paper shows that a simple modification to the Booth-encoding algorithm can be used to increase the probability of a zero coded digit. This increases the probability of a zero in the partial product bits of a Booth-encoded multiplier and reduces the average number of transitions in the partial product bits by 3.75% over the traditional Booth-encoding algorithm for a random input sequence. In addition, we show that the transition probability of carry-bits in the partial product adders is directly related to the transition probability of the partial product bits, and is reduced by approximately 3.75% to 7%. HSPICE simulations show that the proposed encoding can reduce the power dissipation by more than 4% for a 16×16 two´s complement linear array and a Wallace tree multiplier core