Combinatorial architectural level power optimization for a class of orthogonal transforms

In this paper, we present a new technique for low-power architecture synthesis of a class of orthogonal transforms. The core of this technique is based on combinatorial optimization, where the metrics of the graph are computed using architectural level power dissipation (ALPD). The ALPD uses the electrical characteristics of the basic building blocks or intellectual property (IP). Thus, it requires a well-characterized low-power library. The advantage of this technique is the optimal architecture selection at high-level of the design abstraction. We demonstrate this technique for low-power architecture synthesis implementing N-point fast Fourier transform (FFT) and fast wavelet transform (FWT). Moreover we developed a model for low-power library characterization of the arithmetic units, using a linear regression, having an accuracy over 80% when comparing with Spice level simulation