Bandwidth Extension of High-Gain CMOS Stages Using Active Negative Capacitance

A method of extending the bandwidth of a CMOS amplifier by the use of a negative capacitance circuit is presented. Nonideal effects of the negative capacitance circuit are combined with the one-pole amplifier response resulting in a two-pole response. Proper selection of element values leads to a maximally-flat magnitude response with a significantly improved bandwidth for the amplifier. Specific guidelines are given for the design of an effective negative capacitance circuit. Simulations using TSMC 0.25-micron device models show a bandwidth improvement approaching two orders of magnitude in a typical CMOS high-gain stage.