A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism

High reliability requirements in many modern applications make soft errors an extremely important design aspect and pose new challenges in nanometer technologies. In addition, timing faults that may escape fabrication tests become a real concern in high complexity, high frequency designs. To confront this situation, a concurrent error detection and correction circuit and technique are presented in this work. Their application in pipeline architectures is analyzed and the pipeline error recovery mechanism is illustrated. The proposed scheme is characterized by low silicon area requirements, compared to earlier approaches, and the need of only a single clock cycle for pipeline recovery.