An experimental evaluation of neural network approach to circuit partitioning

A methodology for using Hopfield neural networks for circuit partitioning is proposed. The objective function of the neural network is formulated to minimize the cut-size for multiple circuit partitioning. This new objective function is used for partitioning the circuits of standard benchmarks. A comparison of the neural network approach with the other circuit partitioning algorithms such as simulated annealing, Kernighan-Lin and local optimization is carried out. These experiments show that for circuit partitioning, the modified Hopfield network performs similar to local optimization algorithm; however, the neural network approach structurally retains the advantage of easy parallel hardware implementation