Low voltage swing gates for low power consumption

Author

Rjoub, A. ; Koufopavlou, O.

Author_Institution

Dept. of Electr. & Comput. Eng., Patras Univ., Greece

Volume

1

fYear

1999

fDate

36342

Firstpage

234

Abstract

A low swing voltage design technique is proposed. The new design could be used successfully in order to decrease the power dissipation in Complementary Pass-Transistor Logic (CPL) as in Cascade Voltage Switch Logic (CVSL) logic gates. The achieved gate output voltage-level swing reduction, results in a significant reduction of their power consumption. Using the proposed technique, for supply voltage 3.3 V and 0.5 μm CMOS process technology, 35% (for the CPL) and 20% (for the CVSL) power consumption savings is achieved. Improvements in power-delay product are also obtained. In the new gates no special circuit design receiver is required in order to pull-up the low swing signal

Keywords

CMOS logic circuits; VLSI; logic design; logic gates; low-power electronics; 0.5 micron; 3.3 V; CVSL logic gates; LV swing gates; cascade voltage switch logic; complementary pass-transistor logic; low power consumption; low power design; low swing voltage design technique; output voltage-level swing reduction; power dissipation; power-delay product improvement; CMOS logic circuits; CMOS process; CMOS technology; Circuit synthesis; Energy consumption; Logic design; Logic gates; Low voltage; Power dissipation; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.777846

Filename

777846