Title :
High Performance Timing-Driven Rank Filter
Author :
Szántó, Péter ; Fehér, Béla ; Szedö, Gábor
Author_Institution :
Budapest Univ. of Technol. & Econ. Budapest, Budapest
Abstract :
This paper presents an FPGA implementation of a high performance rank filter for video and image processing. The architecture exploits the features of current FPGAs and offers tradeoff between complexity and clock speed. By maximizing the operating frequency the complexity of the filter structure can be considerably reduced compared to previous 2D architectures.
Keywords :
field programmable gate arrays; image processing; median filters; video signal processing; FPGA implementation; high-performance timing-driven rank filter; image processing; video processing; Clocks; Field programmable gate arrays; Finite impulse response filter; Frequency; Gabor filters; Hardware; Image edge detection; Information filtering; Information filters; Sorting;
Conference_Titel :
Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on
Conference_Location :
Nice
Print_ISBN :
1-4244-0395-2
Electronic_ISBN :
1-4244-0395-2
DOI :
10.1109/ICECS.2006.379898
