A high-performance submicron CMOS two-level metal technology incorporating a plasma CVD TEOS interlevel dielectric

Author

Hills, G.W. ; Thoma, M.J. ; Chen, M.L. ; Cochran, W.T. ; Harrus, A.S. ; Lawrence, C.W. ; Leung, C.W. ; Hey, H.P.W.

Author_Institution

AT&T Bell Lab., Allentown, PA, USA

fYear

1988

fDate

13-14 June 1988

Firstpage

35

Lastpage

42

Abstract

The process technology for a fifth generation, high-performance, twin-tub, two-level metal, submicron CMOS technology designed for 5-V custom VLSI applications is presented. Features include high-pressure oxidation, lightly doped drain structures for both n and p channel devices, titanium self-aligned silicide, and plasma-enhanced CVD TEOS (tetraethylorthosilicate) as the interlevel dielectric. Circuits fabricated in this technology include a 64 K SRAM.<>

Keywords

CMOS integrated circuits; CVD coatings; VLSI; integrated circuit technology; metallisation; organic compounds; 64 kbit; SRAM; custom VLSI applications; high-pressure oxidation; lightly doped drain structures; plasma CVD; selfaligned TiSi/sub 2/; submicron CMOS two-level metal technology; tetraethylorthosilicate interlevel dielectric; CMOS process; CMOS technology; Circuits; Dielectric devices; Oxidation; Plasma applications; Plasma devices; Silicides; Titanium; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Multilevel Interconnection Conference, 1988. Proceedings., Fifth International IEEE

Conference_Location

Santa Clara, CA, USA

Type

conf

DOI

10.1109/VMIC.1988.14174

Filename

14174