DocumentCode
2960923
Title
A 1.5 V, 10-bit, 14 MS/s CMOS pipeline analog-to-digital converter
Author
Abo, A.M. ; Gray, P.R.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear
1998
fDate
11-13 June 1998
Firstpage
166
Lastpage
169
Abstract
A 1.5 V, 10-bit, 14.3 MS/s pipeline analog-to-digital converter was implemented in a 0.6 /spl mu/m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak SNDR of 58.5 dB, maximum DNL of 0.51 LSB, maximum INL of 0.66 LSB and a power consumption of 36 mW.
Keywords
CMOS integrated circuits; analogue-digital conversion; integrated circuit reliability; pipeline processing; 0.6 micron; 1.5 V; 10 bit; 36 mW; CMOS pipeline ADC; MOS switches; analog-to-digital converter; bootstrapping technique; device reliability constraints; low voltage operation; Analog-digital conversion; CMOS technology; Digital signal processing; Electric breakdown; Energy consumption; Integrated circuit technology; Pipelines; Switches; Threshold voltage; Video equipment;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-4766-8
Type
conf
DOI
10.1109/VLSIC.1998.688071
Filename
688071
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