Title :
Self-learning neural network LSI with high-resolution non-volatile analog memory
Author :
Morie, Takashi ; Fujita, Osamu ; Uchimura, Keiichi
Author_Institution :
NTT Network Service Syst. Labs., Musashino, Japan
Abstract :
A self-learning analog neural network LSI with nonvolatile analog memory which can be updated with more than 10-bit resolution has been fabricated and tested for the first time. The nonvolatile memory is attained by a new floating-gate MOSFET device which has a charge injection part and an accumulation part separated by a high resistance. The memory retention time is estimated to be over 15 years at 125 C by a baking test. We have adopted in the prototype LSI a partially-serial weight-update architecture in order to reduce the chip area. A prototype chip fabricated using a 1.3-μm double-poly CMOS process includes 50 synapse elements and its computational power is 10 MCPS. The weight updating rate is more than 40 kHz. This LSI can implement deterministic Boltzmann machines and Hopfield networks with Hebbian learning. Backpropagation learning can also be implemented
Keywords :
Boltzmann machines; CMOS analogue integrated circuits; Hebbian learning; Hopfield neural nets; analogue storage; large scale integration; neural chips; unsupervised learning; 1.3 mum; 125 C; 15 y; 40 kHz; Hebbian learning; Hopfield networks; accumulation part; backpropagation learning; charge injection part; deterministic Boltzmann machines; double-poly CMOS process; floating-gate MOSFET device; high-resolution nonvolatile analog memory; memory retention time; partially-serial weight-update architecture; self-learning analog neural network LSI; Analog memory; Automatic testing; CMOS process; Computer architecture; Hebbian theory; Large scale integration; MOSFET circuits; Neural networks; Nonvolatile memory; Prototypes;
Conference_Titel :
Neural Networks, 1995. Proceedings., IEEE International Conference on
Conference_Location :
Perth, WA
Print_ISBN :
0-7803-2768-3
DOI :
10.1109/ICNN.1995.488862
