Design of a fully-static differential low-power CMOS flip-flop

A fully-static flip-flop structure is proposed and compared to both the conventional CMOS flip-flop and the Cascode Voltage Switch Logic (CVSL) static flip-flop proposed by Yuan and Svensson (see IEEE Jour. of Solid-State Circuits, vol. 32, no. 1, p. 62-9, 1997) in terms of speed, power consumption and silicon area. Then an add-and-delay circuit is implemented using all three flip-flop structures to demonstrate the performance of the proposed flip-flop. The add-and-delay structure is chosen since it is a widely used block in digital signal processing. The proposed structure is shown to consume less power and occupy a smaller silicon area. It has the additional advantage of being easier to merge with pass-transistor logic structures