DocumentCode :
2960951
Title :
SAD-Based Stereo Matching Circuit for FPGAs
Author :
Perri, Stefania ; Colonna, Daniela ; Zicari, Paolo ; Corsonello, Pasquale
Author_Institution :
Calabria Univ., Calabria
fYear :
2006
fDate :
10-13 Dec. 2006
Firstpage :
846
Lastpage :
849
Abstract :
This paper presents a novel FPGA-based stereo matching system. The proposed circuit operates on 512times512 stereo images with a maximum disparity of 255. It achieves a 286 MHz running frequency and a frame rate of 25.6 f/s.
Keywords :
field programmable gate arrays; stereo image processing; FPGA; SAD; frequency 286 MHz; stereo images; stereo matching circuit; Cameras; Circuits; Computer science; Field programmable gate arrays; Frequency; Hardware; Layout; Pixel; Registers; Stereo vision;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on
Conference_Location :
Nice
Print_ISBN :
1-4244-0395-2
Electronic_ISBN :
1-4244-0395-2
Type :
conf
DOI :
10.1109/ICECS.2006.379921
Filename :
4263499
Link To Document :
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