A 2.5 V 100 MS/s 8 bit ADC using pre-linearization input buffer and level up DAC/subtractor

Author

Sugawara, M. ; Yoshida, H. ; Mitsuishi, M. ; Nakamura, S. ; Nakaigawa, S. ; Kunisaki, Y. ; Suzuki, H.

Author_Institution

ULSI Device Dev. Labs., NEC Corp., Kanagawa, Japan

fYear

1998

fDate

11-13 June 1998

Firstpage

170

Lastpage

173

Abstract

This paper describes a 2.5 V 100 MS/s 8 bit subranging Analog-to-Digital Converter (ADC). To achieve such low voltage operation and high-speed conversion rate at the same time, a "pre-linearization input buffer" and "level up DAC/subtractor" have been newly developed. These circuits prevent voltage drops on the internal analog signal path and make the supply voltage reduction possible. The ADC also uses a simple encoder scheme "noise immunity encoder" that is resistant to bubbling error for thermometer code.

Keywords

BiCMOS integrated circuits; VLSI; analogue-digital conversion; buffer circuits; encoding; high-speed integrated circuits; integrated circuit noise; 0.25 micron; 180 mW; 2.5 V; 8 bit; A/D convertor; BiCMOS ADC; analog-to-digital converter; high-speed conversion rate; internal analog signal path; level up DAC/subtractor; low voltage operation; noise immunity encoder; pre-linearization input buffer; subranging ADC; supply voltage reduction; voltage drops prevention; Adders; Analog-digital conversion; Circuit noise; Differential amplifiers; Digital circuits; Diodes; Low voltage; National electric code; Ultra large scale integration; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-4766-8

Type

conf

DOI

10.1109/VLSIC.1998.688073

Filename

688073