DocumentCode
2961028
Title
A write-back cache memory using bit-line steal technique
Author
Miyoshi, A. ; Okuyama, H. ; Ozaki, S. ; Tsuki, T. ; Kaneko, K. ; Ogura, S. ; Nishimichi, Y.
Author_Institution
Corp. Semicond. Dev. Div., Matsushita Electr. Ind. Co. Ltd., Kyoto, Japan
fYear
1998
fDate
11-13 June 1998
Firstpage
180
Lastpage
181
Abstract
The authors describe a low-cost high-speed cache memory including a Write Back Buffer (WBB). Since the WBB is located in a cache memory, and connected with memory cells through bit-lines, memory data is copied to the WBB in 1-clock cycle. This cache memory is in a 32 bit microcontroller developed by the authors.
Keywords
CMOS memory circuits; cache storage; 0.35 micron; bit-line steal technique; cache memory; low-cost high-speed memory; microcontroller cache; write back buffer; Cache memory; Consumer electronics; Control systems; Electric variables control; Electrical equipment industry; MOS devices; MOSFETs; Microcontrollers; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-4766-8
Type
conf
DOI
10.1109/VLSIC.1998.688076
Filename
688076
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