DocumentCode
2961053
Title
A 2 MB, 3.6 GB/s back-side bus cache for an IA32 450 MHz microprocessor
Author
Taylor, G. ; Arabi, T. ; Hose, K. ; Jones, J. ; Songmin Kim ; Kuppuswamy, R. ; Mooney, R. ; Price, J. ; Sarangi, A.
Author_Institution
Intel Corp., Hillsboro, OR, USA
fYear
1998
fDate
11-13 June 1998
Firstpage
184
Lastpage
185
Abstract
This paper describes a 450 MHz multichip processor with a 2 MB, 3.6 GB/s level 2 cache. Chips are mounted on both sides of the substrate and use source synchronous, impedance controlled I/O circuits. Mixed voltages are used to allow each chip to take advantage of appropriate technology.
Keywords
CMOS memory circuits; cache storage; microcomputers; microprocessor chips; random-access storage; 2 MB; 3.6 GB/s; 450 MHz; IA32 microprocessor; back-side bus cache; impedance controlled I/O circuits; level 2 cache; microcomputer board; multichip processor; source synchronous I/O circuits; Bandwidth; CMOS process; CMOS technology; Central Processing Unit; Circuits; Clocks; Impedance; Microprocessors; Topology; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-4766-8
Type
conf
DOI
10.1109/VLSIC.1998.688078
Filename
688078
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