Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis

In this paper, based on probabilistic via-connection analysis of single vias and redundant vias, it is well known that on-track redundant via insertion is more important and critical than off-track redundant via insertion for yield optimization. Furthermore, a two-phase insertion approach for yield optimization is proposed to insert on-track redundant vias by finding a maximum matching result in a bipartite graph and insert off-track redundant vias by using a maximum constrained edge-pair matching result in a constrained edge-pair matching with via-sharing constraints. According to the Poisson yield model for redundant via insertion, the experimental results show that our proposed two-phase insertion approach can increase 0.3%~7.4% wirelength to improve 4.3%~44.8% chip yield for the tested benchmarks.