Simulation of SoCs with embedded mixed-signal Cores using a Verilog High-Speed Virtual Serial Interface

In SoCs (system-on-chip) with mixed-signal cores, both the functional behavior and the production tests should be simulated at top level before tape-out. The use of behavioral models for the analog and mixed-signal cores enables simulation of the whole signal path including the analog inputs or outputs of the mixed-signal cores. Since many SoCs are described in the Verilog HDL (hardware description language) and since Verilog does not permit analog values on wires, the analog values have to be converted into high-speed serial binary data streams. This requires a virtual serial interface, which is described in this paper. The interface has been extended to enable the simulation with analog as well as digital signals, equivalent to the use of analog and digital tester channels.